EE 603 Power Electronics

 

Homework # 9          Due April 10, 2006

 

 

 

Problem 1

This is a repeat of problem 1 in homework 8. After this weeks lectures it should make more sense. The solution to homework 8 including Spice files are on the web. Study the results to be sure you can answer the questions in problem 1 yourself. A schematic of the basic step down converter is shown in Fig. 1.

 

Fig. 1  Basic step down converter.

Let Vin equal 160V and Vout equal 80V. The load is 3A. The MOSFET switching frequency is 25kHz, L = 3mH, C = 0.1mF and Rg = 800W. The diode has an Iss= 9 10-14A, Cjo= 100pF, and TT= 100ns with all of the other diode Spice parameters at their default values.

 

a)     What are Cin, Cr, and Cout for the IRF510 MOSFET? Note Cin = Cgs, Cr = Cgd, and Cout = Cds.  Use the IRF510 specification.

b)     What are Vtr and Kp for the IRF510 MOSFET at 25C? Use the typical drain characteristics in Fig. 1 of the IRF510 specification and the VGS = 5V curve.

c)      What is the IRF510’s drain resistance (RD in the level 1 Spice model) based on the specified on resistance and your calculated channel resistance?

d)     If the channel is 1mm long what is the IRF510’s W?

e)     Estimate the initial capacitor voltage and inductor current.

f)       Make a Spice model of the above circuit using a level 1 MOSFET model with your W, and threshold values from above. Insert the MOSFET capacitances as separate external capacitances. Specify the inductor and output capacitor initial conditions. Make the input a pulse voltage from 0V to 15V with rise and fall times equal to 10ns.

g)     Estimate the step size you should use.

h)     Simulate your circuit for two switching cycles. Plot the inductor current and diode voltage for two cycles. If your drain current oscillates, try going to the convergence options sub-menu in the simulation menu and setting the integration method to Gear. If this does not fix your problem, try reducing the step size.

i)        Plot the gate voltage, drain to source voltage and drain current showing their timing relationship. Expand your results, first about turn on and then about turn off, to show the turn on and turn off transients. You may define a new waveform equal to VDS / 10 and plot it with the gate voltage and the drain current so they all fit on the same scale.

j)        Compute the turn on and turn off times analytically. How do they compare to the Spice computed results?

k)      Estimate the switching energies and the average switching losses.

l)        Estimate the conduction losses.

m)   Using the IRF510 specification, find the device’s thermal resistance. Estimate the temperature rise junction to case, case to sink and case to ambient. Does the IRF510 require a heat sink in this application?

n)     Why is the Miller time for turn on less than the Miller time for turn off?

o)     Add the stray inductance in Fig. 2 and its corresponding loss resistance. Let Lstray = 1mH and Rloss = 1KW.

p)     Simulate your circuit for two switching cycles. Plot the gate voltage, drain to source voltage and drain current showing their timing relationship. You may define a new waveform equal to VDS / 10 and plot it with the gate voltage and the drain current so they all fit on the same scale.

q)     Use the permeability of free space () to estimate the length of wire from the Vin source to the diode and MOSFET required to get 1mH of inductance.

 Fig. 2  Basic step down converter with stray inductance.

 

 

 

Problem 2

 

A schematic of the basic building block of many power electronic circuits including DC / DC converters and motor controllers is the phase leg or equivalently the half bridge circuit shown in Fig. 3. Note the diodes shown explicitly in Fig. 3 are inherent to the structure of a power MOSFET and thus are not separate diodes. For other power semiconductors, such as bipolar transistors, separate diodes would be required. One challenge of this circuit, is generating the gate signal (0V-15V) for the upper MOSFET when Vin is large, say 150V. This is because its source is not referenced to ground and the MOSFET’s gate to source voltage should not be much more than 15V with 30V a maximum. This problem can be solved by coupling the gate voltage for the upper MOSFET through a transformer or by using a circuit called a bootstrap circuit. A simplified schematic of the bootstrap circuit driving a phase leg with a simple

 

Fig. 3  Phase leg or half bridge circuit.

 

Load is shown in Fig. 4. Compare the schematic of bootstrap circuit in Fig. 4 bootstrap circuit shown in the specification for the commercial IR2110 integrated circuit to see improvements that the designer of the IR2110 made to this simplified circuit.

 

a)    Which MOSFETs in Fig. 4 are p-channel and which are n-channel (there are a total of 9 MOSFETs)?

b)    What is the required minimum VDS rating of each MOSFET in the schematic in Fig. 4 (there are a total of 9 MOSFETs)?

c)     Which MOSFETs in Fig. 4 are high voltage power MOSFET, high voltage signal MOSFETs, and low voltage signal MOSFETs (there are a total of 9 MOSFETs)?

d)    What is the purpose of D2?

e)    What is the minimum required reverse voltage rating of D1 and D2?

f)      How would you size Rch and C1?

g)    What determines the value of R1?

h)    The resistor R2 is not absolutely necessary, why is it there and what is its maximum value in terms of R1?

i)       Estimate the maximum plus gate to ground and gate to source voltage on MOSu. Estimate the minimum gate to ground and gate to source voltage on MOSu.

j)       Build a Spice model of the circuit in Fig. 2 and simulate it for 200us using a 100ns step size. Plot VGd V(IVGU), and V(IVUBFIN) over this time interval. Have Spice do an operating point analysis to compute the initial conditions for the circuit. Use the spice default diode for the diodes with Cjo = 1e-10 F. The MOSFET parameters for MOSu and MOSd are level one MOSFET model, Vt = 3V, Kp = 0.5 A/V2, cbd = 1 10-12F, cbs = 1 10-12F, and tox= 0.5 10-7m. The nmos MOSFET parameters for MOSo, MOS3, MOSnu, and MOSNd are level one MOSFET model, Vt = 3V, Kp = 2e-4 A/V2, cbd = 1 10-12 F, cbs = 1 10-12 F, and tox= 1 10-7m. The pmos parameters for MOSpu, MOSpd, and MOS are level one MOSFET model, Vt = -3V, Kp = 2e-4 A/V2, cbd = 1 10-12 F, cbs = 1 10-12 F, and tox= 1 10-7m. Let Vind be a pulse with parameters V1 = 0V, V2 = 15V, Td = 0 s, tr = 1u, tf= 1u, Pw = 20u, and period = 80u. Let Vinu be a pulse with V1 = 0V, V2 = 15V, Td = 40us, tr = 1us, tf= 1us, Pw = 20us, and period = 80us.

 

 

 

 

Fig. 4  Simplified schematic of the bootstrap circuit.