PAL Reference Materials

The following reference materials on PAL devices have been collected/created by H. Dietz in Fall 1999 for the personal use of students taking EE481. The section on simulation was added by W. Dieter in Fall of 2001.

Overview Of The 22V10

The 22V10 PAL, shown above, is one of the simplest and most commonly used forms of "programmable logic device." In a 24-pin DIP, it provides 22 pins that can be used to connect to the internal logic, 12 usable only as inputs and 10 configurabale as either inputs or outputs. Yes, that's where the name comes from: 22 user I/O pins, up to 10 of which can be outputs.

The internal logic consists of a fairly generic collection of gates and "macrocells" that are arranged so that the connections between them can be configured using a built-in flash memory (electrically reprogrammable read only memory). Thus, a 22V10 will retain its configuration until it is reprogrammed.

Although the interconnection pattern shown above is very general, and the programming software allows you to write your design without worrying about how it will be implemented within the chip, there are restrictions on how complex a circuit you can implement within a single 22V10 part. These restrictions come primarily from the way that the clock line is distributed and the configuration of the logic within each macrocell. Each macrocell looks like:

The precise internal organization of the 22V10 PAL is described in more detail in this PDF file. It is important to note that there are many variations on the 22V10; the comments made here apply specifically to the PALCE22V10 parts that we use in the lab.

Notice that all of the flip-flops contained in the part share a single common clock line, which must be pin 1. If you don't need a clock, you can use pin 1 as an ordinary input, but no other pin or signal can be used as a clock within the part.

Programming The 22V10

The programming of a 22V10 is actually a fairly complicated thing, because you need to map your circuit design into the logic within the chip. Fortunately, there are a variety of good tools that can perform this mapping for you. Using these tools, you simply specify the circuit you want and an optimizing compiler rearranges your specification and encodes it as bit patterns that you download (burn) into the chip.

Sometimes, the compiler might not be smart enough to rearrange things even though the logic could fit; in these cases, you might need to re-write your specification to better match what's inside the chip. Still worse, some designs are simply too complex to fit in a 22V10 no matter how you express the logic -- for those, you need to get "bigger" programmable logic devices or to partition your design into multiple 22V10 parts.

For many years, the standard language and compiler for 22V10 logic has been PALASM, from Lattice/Vantis. A local copy of the files has been placed here to avoid network problems:

manual.pdf, 1698751 bytes
paldisk1.zip, 662958 bytes
paldisk2.zip, 1124673 bytes
paldisk3.zip, 1065232 bytes
paldisk4.zip, 1092626 bytes
paldisk5.zip, 225877 bytes
patch1.zip, 109775 bytes
patch2.zip, 233947 bytes
readme.txt, 5626 bytes

The PALASM syntax for simple logic expressions is very straightforward; take a look starting at page 125 of the manual.pdf file. Generally, there is one statement per line. The most important components of a PALASM file are:

CHIP name partnumber

Where partnumber must be the name of the particular programmable part and name can be whatever name you wish

PIN number signal

Where number is the number of a particular I/O pin and signal is the name that you will use for that signal in your equations

EQUATIONS

Separates the equations from the pin definitions

signal = expression
signal := expression

Equations are written like assignment statements in most computer languages. However, you can use either = or := for the assignment; = means combinational, := means that the assignment is REGISTERED (i.e., only changes with a clock pulse). Some of the more useful operators are: * AND, + OR, :+: XOR, and / NOT; parenthesis can be used for grouping.

In addition to PALASM, there are various other logic compilers that can target the 22V10 family. For example, VHDL, Verilog, and Lola. In general, they all look and work pretty much the same, with about as many differences between them as there are between Fortran, C, and Java.

There is a programmer in the lab (581 AH) that can be used to download/"burn" data into a 22V10.

Simulating a PALASM Design

PALASM requires the CHIP section, in which you specify which pins your program will use, and the EQUATIONS section, in which you specify the equations that define the chip's outputs. PALASM also allows you to provide a SIMULATION section to let you verify that your design will produce the outputs you expect without ever wiring up the chip. Basically you tell PALASM what you think the outputs should be for a given set of inputs.

SIMULATION

Separates the simulation section from the equations and pin definitions

TRACE_ON signal1 signal2

Lists the signals that will be simulated

SETF signal1 /signal2

Set signal1 to a 1 and signal2 to a 0. Only inputs can be set.

CHECK signal3 /signal4
CHECKQ signal5 /signal6

CHECK and CHECKQ verify that the specified signals are true. CHECK is for combinatorial output signals and CHECKQ is for registered outputs. In this case CHECK is verifying that signal3 is 1 and signal4 is 0.

TRACE_OFF

Indicates the end of tracing

Examples

Several example PALASM files are available on the EE 481 web site to demonstrate the correct PALASM syntax.