Hardware Description Languages and Programmable Logic
Instructor: Dr. J. Robert (Bob) Heath
Office: 313 Electrical Engineering Annex ((859)257-3124)
Web Page: http://www.engr.uky.edu/~heath
Office Hours: M (4:00 p.m. - 5:00 p.m.)
W (3:00 p.m. - 4:00 p.m.)
F (1:00 p.m. - 2:00 p.m.)
Text: 1. Sudhakar Yalamanchili, Introductory VHDL From Simulation to Synthesis, Prentice Hall, 2001.
2. Xilinx Inc., FoundationTM Student Edition 2.1i Series Simulation and Synthesis Software, Prentice Hall (On CD-ROM Within Text # 1).
Meeting Schedule: MWF (12:00 p.m. - 12:50 p.m.) 265 AH
Course Objectives: The objectives of this course are to provide students with a working knowledge required to describe student developed digital logic system designs in Hardware Description Languages (HDLs) at behavioral, register, and structural levels; to verify their logic system designs via pre-synthesis HDL simulation; and to then synthesize/implement their final digital logic system designs to Complex Programmable Logic Devices and/or Field Programmable Gate Arrays for experimental testing and final design and operational verification. To meet these objectives, the following competencies should be imparted to the students:
1. An understanding of behavioral, register, and structural level HDL based modeling, simulation, and synthesis/implementation processes and their impact on the design and manufacturing processes.
2. An understanding of programmable logic implementation media, programming techniques, and architectures and their impact on the design, synthesis, implementation, testing, and manufacturing processes.
3. The ability to develop behavioral, register, and structural models for digital circuits and verify/debug those models through high level simulations.
4. The ability to synthesize behavioral, register, and structural models and to implement and experimentally test the resultant design in programmable logic devices.
5. Hands-on experience with Computer-Aided Design (CAD) tools for design capture, verification and synthesis/implementation of HDL models as well as tools for generating configuration data, programming, and testing the target programmable logic devices.
Course Outline: I. Digital System Design Flow and Hardware Description Languages (HDLs).
II. Very High Speed Integrated Circuit Hardware Description Language (VHDL).
III. Verilog and Other HDLs.
IV. Modeling Digital Systems.
Homework: Homework will be periodically assigned. You will be provided solutions to
all homework problems. You must work “all” homework problems to
do well in this course.
Projs: During the semester you will design several digital systems, capture
each design using VHDL, verify correct design and functional/timing operation of each logic system via pre-synthesis VHDL sumulation, synthesize and implement your design to a Xilinx FPGA chip on a demonstration board and perform experimental testing of your synthesized design as a final level of correct design and operational verification. A brief computer generated project report will be prepared for each design and design verification project.
Example design, design verification, synthesis, implementation, and experimental testing projects would include initially combinational logic circuits/systems, sequential logic circuits/systems, followed by more complex digital systems such as small general purpose and/or special purpose computational systems or their functional units.
Grade: 1. Two (2) Tests: (Sep. 24 and Nov. 12) - 50%
2. Design, Design Verification, Synthesis, Implementation, and Experimental
Testing Projs. - 30%
3. Comprehensive Final Examination (Dec. 12)- 20%
Your final grade will be determined by the number of points you
have earned from 100 possible as follows:
A: 90 - 100 pts.
B: 80 - 89 pts.
C: 70 - 79 pts.
D: 60 - 69 pts.
E: < - 60 pts.
Examinations: Make-up examinations will only be given to students who miss
examinations as a result of excused absences according to applicable
current university policy. Make-up examinations may be in a different format from the missed examination such as an oral exam, etc.
Class Attendance: Attendance of all class lectures is required to assure maximum course
performance. You are responsible for all business conducted within a class. Daily attendance rolls will not be taken.
Cheating: Cheating will not be allowed or tolerated. Anyone caught cheating will be dealt with according to applicable University policy. (Assignment of a grade of E for the course).