EE 581-001
COMPUTER ORGANIZATION AND DESIGN II
COURSE SYLLABUS

INSTRUCTOR : Dr. J. Robert Heath

OFFICE : 310 Electrical Engineering Annex (257-3124)

E-MAIL ADDRESS : heath@engr.uky.edu

OFFICE HOURS :

M (11:00 am - 12:00 noon)
W (3:00 pm - 4:00 pm)
R (2:00 pm - 3:30 pm)

D.A. Patterson and J.L. Hennessy, Computer Organization and De sign: The Hardware/Software Interface, Second Edition, Morgan Kaufmann, 1998.

REFERENCE :

M.M. Mano, Computer System Architecture, Third Edition, Pren tice-Hall, 1993.

S.G. Shiva, Computer Design and Architecture, Second Edition, Harper Collins Publisher Inc., 1991.

L.L. Wear, J.R. Pinkert, L.C. Wear, and W.G. Lane, Comput ers: An Introduction To Hardware And Soft Ware Design, McGraw-Hill, 1991.

V.P. Heuring and H.F. Jordan, Computer Systems Design and Ar chitecture, Addison Wesley, 1997.

J.P. Hayes, Introduction to Digital Logic Design, Addison Wesley, 1993.

K. Skahill, VHDL for PROGRAMMABLE LOGIC, Addison Wes ley, 1996.

S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Sun Soft Press, Prentice Hall, 1996.

SILOS III USER'S MANUAL, Simucad, Inc.Union City, CA, 1997.

MEETING SCHEDULE : T, R (12:30 pm - 1:45 pm) 453F AH

COURSE DESCRIPTION :

Design and verification methodology for general purpose programmable digital computers. Design, verification, and per formance evaluation of general purpose programmable register/register, register/memory, and memory/memory architecture computers. Includes design of assembly language instruction set, datapath, controller, memory, and input and output structures and where applicable, interrupt and direct memory access struc tures. Pipelining of computer designs. Design methodology and design and performance evaluation of special purpose computer systems. Design verification using Hardware Description Lan guages (HDLs). Team design and evaluation projects. Prereq: EE 280 and EE/CS 380.

TOPICAL OUTLINE :

1. Instruction Set Architecture of a general purpose programmable digital computer.
2. Register/register, register/memory, and memory/memory ar chitecture general purpose programmable digital computers.
3. General purpose programmable digital computer design and verification methodology.
4. Instruction set design.
5. Datapath design.
6. Controller design (hardwired and microprogrammable).
7. Pipelining a design for performance enhancement.
8. Structural, data, and control hazards and their elimination.
9. Memory hierarchy design.
10. Main memory design.
11. Cache memory design.
12. Virtual memory.
13. Effect of hierarchical memory system on computer perfor mance.
14. Input/output, interrupt, and direct memory access structures.
15. Input/output performance measures.
16. Types and characteristics of input/output devices.
17. Input/output busses and interfacing input/output devices to the memory, processor, and operating system.
18. Design verification using Hardware Description Languages (HDLs).
19. Team design projects of representative register/register, reg ister/memory, memory/memory architecture computers.
20. Special purpose digital computers (state machines).
21. Design and verification methodology of special purpose digital computers.
22. Team design projects for special purpose digital computers.

1. Two tests (25% Each). (Feb. 18, Apr. 10)
2. Homework (taken up: no grade)
3. Team design projects
4. Comprehensive final exam at time scheduled by University

Tests and the final exam will be graded on a 100 point basis;

Team design projects on a 25 point basis. Some homework as signments will be taken up but not graded. Whether you have turned in the complete homework assignment will be recorded and used in ``tie breaker'' situations related to determination of grade scale cut-off points. Your final grade will generally be determined by the number of points you have accumulated from 100 total possible points as follows:

90 - 100 pts.
80 - 89 pts.
70 - 79 pts.
60 - 69 pts.
below 59

An equitable grade scale will be applied when warranted.

MAKE-UP EXAMINATIONS :

Make-up examinations will only be given to students who miss examinations as a result of excused absences according to ap plicable university policy. Oral make-up examinations may be given.

Cheating will not be allowed or tolerated. Anyone caught cheat ing will be dealt with according to applicable university policy. (Assigned a grade of E for the course).

CLASS ATTENDANCE :

Attendance of all class lectures is required to assure maximum course performance. You are responsible for all business conduct ed within a class.

HOMEWORK, TEAM DESIGN PROBLEMS :

Homework and team design problems will be periodically assigned. Assignments are due at the beginning of the class period on due dates. Late assignments can not be accepted.