EE 499 - 003
EE Design:
Computer Design and Implementation
Course Syllabus
Fall, 1998

Instructor:

Dr. J. Robert Heath

heath@engr.uky.edu

http://www.engr.uky.edu/~heath

310 Electrical Engineering Annex (257-3124)

Office Hours:

M (11:00 am - 12:00 noon)
W (1:00 - 2:00 pm)
F (2:00 - 3:00 pm)

References:

D.A. Patterson, J.L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Second Ed., Morgan Kaufmann, San Mateo, CA, 1998.

AT&T Field-Programmable Gate Arrays Data Book, AT&T Microelectronics, April, 1995.

Viewlogic, Inc WORKVIEW OFFICE and Lucent Technolo gies, Inc FOUNDARY CAD/CAE Manuals, 1997

W. Stallings, Computer Organization and Architecture: Designing for Performance, 4th. Ed., Prentice -Hall, Inc. 1996.

R.E. Haskall, Introduction to Computer Engineering: Logic Design and the 8086 Microprocessor, Prentice-Hall, Englewood Cliffs, NJ, 1993.

G.H. Miller, Microcomputer Engineering, Prentice Hall, En glewood Cliffs, NJ, 1993.

J.S. Byrd, R.O. Pettus, Microcomputer Systems, Architecture and Programming, Prentice Hall, Englewood Cliffs, NJ, 1993.

S.G. Shiva, Computer Design and Architecture, 2nd. ed. Harper Collins Publishers Inc. 1991.

V.P. Heuing and H.F. Jordan, Computer Systems Design and Architecture, Addison Wesley, 1997.

Meeting Schedule:

MWF (3:00-3:50pm) AH251 and Computer Architecture Laboratory (AH556)

Course Description:

Design teams will be formed and each team will design, then implement/synthesize/build, and finally, test and performance eval uate a general purpose programmableble digital computer. The computers may be either Reduced Instruction Set Computer (RISC) (register/register),Complex Instruction Set Computer(CISC) (mem ory/register), or memory/memory architecture. Designs will be im plemented using Complex Programmable Logic Device (CPLD) or Field Programmable Gate Array (FPGA) integrated circuit chip technology. The design process will consist of first designing the computers assembly language instruction set (16 instructions), fol lowed by the design of the computers datapath, controller, memory, input/output structure, interrupt system, and a minimal operating system. Each design team will then verify their design via simulation using Viewlogic, Inc's WORKVIEW OFFICE CAD tools and then synthesize(implement) their design to a FPGA chip using Lu cent Technologies, Inc. ORCA FOUNDRY CAD synthesis tools. The synthesized computer will then undergo final testing by having it run a series of short test programs written in the Assembly Lan guage of the computer. Each design team will determine the perfor mance of their implemented computer and compare this perfor mance to that of the computers of other design teams. Each design team must design, synthesize, and successfully test a working com puter to complete the course.

1. Ability to effectively work in groups to develop and propose engineering solutions.

2. Ability to apply previously acquired engineering principles as well as learn new principles in solving a large engineering system specification, design, synthesis (implementation), and verification problem.

3. Ability to experimentally verify that a proposed, designed, and synthesized (implemented) engineering system meets original design, operational, and performance specifications.

4. The ability to communicate and throughly document the results of an engineering design project to the engineering community using a variety of media (report, web page, etc.).

1.	Assembly Language Instruction Set Design	10%
2.	Gate and Register Level Design of Computer	20%
3.	Theoretical Performance Evaluation of Computer	5%
4.	Synthesis/Implementation and Testing of Computer	30%
5.	Experimental Performance Evaluation of Computer	15%
6.	Design Presentations and Final Project Report	20%

Your final grade will generally be determined by the number of points you have accumulated from 100 possible points as follows:

A: 90 - 100 pts.

B: 80 - 89 pts.

C: 70 - 79 pts.

*An equitable grade scale will be applied when warranted.

Cheating will not be allowed or tolerated. Anyone caught cheating will be dealt with according to applicable University policy. (As signment of a grade of E for the course).

Class Attendance:

Attendance of all class lectures is required to assure maximum course performance. You are responsible for all business conducted within a class.

Homework, Laboratory Assignments:

Homework and laboratory assignments will be periodically made. Assignments are due at beginning of the class period on due dates. Late assignments cannot be accepted.