This document contains a step-by-step tutorial for generating the layout of an inverter in the Mentor Graphics application IC Station. It covers opening IC station and creating a cell, generating layout, and checking the design for errors (DRC and LVS). Documents covering extracting parameters for analog simulation and advanced tip for editing cell layouts are also linked below. Separate documents began and continue the tutorial for other Mentor applications.
At this time, you should have completed schematic entry in DA and functional simulation in Quicksim. You should also have created the design viewpoint for your inverter cell. You should also be familiar with the mask layers and design rules which are covered in DRC Rules.
Note, throughout this tutorial we have used both L and l to represent the minimum feature size lambda.
the design for IC station:
The dve script
that you ran for simulation also creates the viewpoints needed for layout and
verification. You only have to do this once per design. Even if you make changes
to your design you don't have to do this again. If you do, the script will do
nothing and that's OK. If you decide to change the technology,
however, you must rerun the script with the appropriate technology parameter.
Up IC Station:
on the Navigator button under Attach
Library then click on the 4-direction arrows and enter the directory
Follow the same procedure for Process and select 'ami05' (choose the file with the 'P' icon, not the folder icon).
the Rules File, click on the Navigator set
the directory (using the 4-direction arrow button) to
Returning to the Create Cell window, keep the default Angle Mode and Cell Type, but under Connectivity select 'With connectivity'.
the EDDM Schematic Viewpoint as
Finally, click 'OK' in the Create Cell window to create your inverter cell
When your cell opens (at first, it will be a blank layout sheet), notice the main IC palette on the right. You will use this to access many of the IC functions.
From the DLA Layout palette, click
Top to return to the main IC Palette.
From the DLA Layout palette, click Top to return to the main IC Palette.
2. Beginning Transistor Layout:
3. Adding Shapes
You can either select a layer by clicking on it or you can type the name of the layer in the Or Type In box. Click the 'Keep Option Settings' button if you want this layer to be the default layer (i.e., it will automatically be selected each time you use the Add Shape command). Use the scroll bar to move down to layer 43, ACTIVE. Select this layer and click OK.
Scroll down the list to find the layer you want. Start by choose the active layer. Click on active and then click OK. The mouse pointer changes to + format. In the layout cell window, click and drag to form a rectangle that is 15L (width) x 5L (height). At this point the polygon is selected and will appear as an unfilled rectangle. Press F2 to unselect the object and it will fill with the pattern for that layer.
The function keys, in combination with shift/control/alt, provide you with many commands that you will use often. These are shown at the bottom of the IC window. Practice using the functions, Select, Unselect, Move, and Copy. When you are done, save only one ACTIVE rectangle and delete all others.
Adding more layers:
Continue selecting new layers and adding to form the transistor. Cover the ACTIVE layer with a N_PLUS_SELECT (which we'll call N-SELECT) layer to begin forming an nMOS transistor (notice we do not have a N-Well layer, consistant with an nMOS device). The N-SELECT layer should overlap the ACTIVE by 2L on all sides (determined by design rules). The region where POLY overlaps the ACTIVE layer with N-SELECT forms the n-type MOS Gate. To form a p-gate we would need an N-Well and would replace N-Select with P-Select.
Note there are many editing functions that allow you to cut, notch, stretch, etc. any polygon you draw. You will need to become familiar with many of these functions. More information on these is provided in a supplement document Editing Cell Layout. If you practice these functions, make sure you have only the layers specified above when you return to this part of the tutorial.
To form a substrate tap, you will need a combination of the layers ACTIVE and P-SELECT. Add a tap now. Later we will want to form an n-well tap, which will need a combination of ACTIVE and N-SELECT inside an N-WELL layer. These taps are also called pdiff and ndiff.
For this tutorial, right now you should be trying to build a single nMOS transistor with associated substrate tap. It should look like the figure to the right, except without contacts and metal which will be added later. Make your layout look like the figure before moving on.
point, let's save the cell so we don't lose any work incase of computer crash
or other acts of God. Select
can continue, we need to reserve our cell. Every time we save the cell, it
will no longer be reserved for edit. So, if you want to modify your cell
(and you do!), select
5. Checking the layout:
Note: This first time through the DRC check, you will get one or more 'bad_contact' (or similar) errors. Ignore these for now; you will fix them in the next step.
Consider first the nMOS transistor. Since this is an n-well CMOS process, the nMOS transistors must be formed in the p-substrate with an associated substrate contact called a tap. The substrate will be connected to the ground or VSS of the circuit. The source of the nMOS transistor will also be connected to ground, and the drain of the transistor will (eventually) be connected to the output node.
Using the ACONT (CONTACT_TO_ACTIVE) layer, add contacts to the source and drain following the Adding Shapes step above. Next add a contact to the tap active layer. Then, add a METAL1 layer across the bottom of your transistor, covering the tap contact and stretching across the full width (left-to-right) of the P-SELECT layer. This will form the ground power supply rail in your design (discussed more in the note below). You should make the METAL1 ground rail as wide as the tap active layer (5L). Although this is larger than the minimum size of metal1, we want the ground (and VDD) rails to be able to handle more current and therefore be wider than minimum size.
Finally, you need to connect the source of the transistor to the ground rail using METAL1. You can either add a new polygon to connect the source contact (left side of the transistor) to the tap contact, or you can try the notch command to modify the metal1 power rail polygon. Either way, make sure your source and substrate tap are connected.
When you are done, your cell should look very similar to the figure above. Save your cell and then reserve it for edit before continuing.
Do it All Again
Note about cell pitch. In large-scale VLSI design (i.e., with many transistors/gates/cells), it is important to make the cell layouts have uniform height so that they will match when placed side-by-side. Typically, we will design each gate with a VDD rail at the top and a Ground rail at the bottom. If we place two cells together, we want these power rails to match-up. This will make more sense when we start putting together several gates later in the course. We define pitch as the distance from top to bottom of our layout cell, measured from the top if the VDD rail to the bottom of the Ground rail. For this course, we will use a cell pitch of 50l. Some larger cells might not match this size, but all the basic logic gates should have a layout height of 50l.
8. Final Layout Steps
Since we often want to connect to the input gates from metal1, you should add a metal1 contact to poly on your input. Notch your POLY input near the middle of the cell to be at least 5Lx5L, add METAL1 on top of this, then add PCONT (CONTACT_TO_POLY) in the center of these shapes. The final layout should be very similar to that shown below.
Once you think you have the layout complete, you should check for DRC errors and fix them before continuing. Jump to Design Rules Checker then come back here and continue.
9. Adding the ports
With the desired layer
selected, to make the port, use the
main menu to select
For an input
Port Type = Signal;
Direction = in; Port Name = in,
then click OK.
(Use in rather than in1 which is shown in the
(Use in rather than in1 which is shown in the figure).
Repeat for the output port (unselect the input first!) setting Port Type = Signal; Direction = out; Port Name = out, then click OK
We also need to make
ports of our power and ground rails. To make the VDD
select metal1 layer across the top of your cell and go to
Repeat for the ground power port selecting the metal1 layer at the bottom of your cell and naming it ground.
Finally, unselect all everything by hitting the F2 key.
10. Adding Property Text
11. Setting the cell
Very Important: Once you instantiate a layout cell into a higher-level cell, you should NOT change the origin as this will cause the cell to shift within the higher-level cell disrupting any connections you would have made.
During this tutorial, you will be asked to jump down to this section and complete a few step before going back to continue above. However, after you complete the previous section, you should go through the DCR check one more time and then complete the LVS steps outlined below before continuing to the Extraction section.
Design Rule Checker
To go back to the Generating Layout part of the tutorial, click here.
LVS( Layout Vs Schematic):
still in the IC Trace (M) palette, select
The LVS checker will begin comparing your layout to your
schematic. When this is done, you will see that ‘mask
results database loaded’ appears at the bottom of the screen. Select
Before you finish, you MUST PASS LVS and get a smiley face.
Important: be sure to close the LVS report
before running another LVS. Otherwise, the old report will not be
overwritten and you will see the old LVS report when you open it.
Although you must fix all
errors, you can ignore the warning about
bad devices in the layout.
Once you have successfully passed
LVS, you should save your cell. Select