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Design Rules (DRC)
for the AMI 0.5mm
Process
Layer Names
Layer
|
Name
|
CIF Alias
|
GDS Number
|
|
n-well
|
nwell
|
CWN
|
42
|
|
active (s, d, gate)
|
active
|
CAA
|
43
|
|
polysilicon
|
poly
|
CPG
|
46
|
|
n-diffusion and n-tap
|
nplus
|
CSN
|
45
|
|
p-diffusion and p-tap
|
pplus
|
CSP
|
44
|
|
metal1-to-active contact
|
acont
|
CCA
|
48
|
|
poly-to-metal1
|
pcont
|
CCP
|
47
|
|
first metal
|
metal1
|
CM1
|
49
|
|
metal1-to-metal2 contact
|
via
|
CV1
|
50
|
|
second metal
|
metal2
|
CM2
|
51
|
|
bond pad contacts
|
glass
|
COG
|
52
|
|
non-active layer
|
comments
|
CX
|
---
|
Selected Design
Rules
The following
are a reduced set of design rules (actual DRC file contains many more rules)
that will be used for all designs in this course.
We will be designing with ‘lambda-based’ rules where ‘L’ in the
rules below stands for ‘lambda’ and is equal to 0.3mm.
N-well
DRC1_1 {
@ N-Well width = 12L}
DRC1_2 { @ N-well spacing (different potential) = 18L}
Active
DRC2_1 {
@ Active area width = 3L}
DRC2_2 { @ Active area spacing = 3L}
DRC2_3 { @ Source/Drain Active to Well Edge = 6L}
DRC2_4 { @ Substrate/Well Contact, Active to Well Edge = 3L}
poly
DRC3_1 {
@ Poly width = 2L}
DRC3_2 { @ Poly spacing = 3L}
DRC3_3 { @ Gate poly overlap of active = 2L}
DRC3_4 { @ Active overlap of gate poly = 3L}
DRC3_5 { @ Field poly to active = 1L}
Nselect & Pselect
DRC4.1p
{ @ nselect overlap of gate > 3L}
DRC4.1n { @
pselect overlap of gate > 3L}
DRC4.2 {
@ select overlap of active > 2L}
DRC4.3p { @
pselect overlap of actcont > 1L}
DRC4.3n { @
nselect overlap of actcont > 1L}
DRC4.4pw {
@ P_PLUS_SELECT width > 2L}
DRC4.4ps {
@ P_PLUS_SELECT space > 2L if NOT CONNECTED}
DRC4.4nw { @
N_PLUS_SELECT width > 2L}
DRC4.4ns { @
N_PLUS_SELECT space > 2L if NOT CONNECTED}
DRC4.5np { @
no overlap between N_PLUS_SELECT and P_PLUS_SELECT }
Contact to poly
DRC5_1 {
@ Contact to poly size exactly 2L X 2L}
DRC5_2 { @ Poly overlap for contact = 1.5L}
DRC5_3 { @ Contact to poly spacing = 3L}
DRC5_4 { @ Contact to active space to gate of transistor = 2L}
Contact to active
DRC6_1 { @ Contact to active exactly 2L X 2L}
DRC6_2 { @ Active overlap for contact = 1.5L}
DRC6_3 { @ Contact to active spacing = 3L}
DRC6_4 { @ Contact to active space to gate of transistor = 2L}
Metal1
DRC7_1 {
@ Metal1 width = 3L}
DRC7_2 { @ Metal1 spacing = 3L}
DRC7_3 { @ Metal1 overlap of contact to poly = 1L}
DRC7_4 { @ Metal1 overlap of contact to active = 1L}
Via
DRC8_1 {
@ Via size exactly 2L X 2L}
DRC8_2 { @ Via spacing = 3L}
DRC8_3 { @ Via overlap by METAL1 = 1L}
DRC8_4 { @ Via spacing to contact = 2L}
Metal2
DRC9_1 {
@ Metal2 width = 3L}
DRC9_2 { @ Metal2 spacing = 4L}
DRC9_3 { @ Metal2 overlap of via = 1L}
Bad Layout
Rules
The following
lists several cases that will be flagged for improper layout.
bad_active_area
{ @ Active area must be covered by a select}
bad_contact_poly { @ Contact to poly must consist of poly, CONTACT_TO_POLY, and METAL1}
bad_contact_active { @ Contact to active must consist of active}
bad_contact_gate { @ Contact to poly may not be on gate region}
bad_via {@ Via must consist of METAL1, via, and METAL2}
bad_contact_via {@ Via must NOT be stacked with contact}
select_overlap { @ Overlap of N+ and P+ not allowed}
bad_nwell { @ Nwell must have well contact}
bad_psubstrate { @ Psubstrate must have a substrate contact}
bad_pgate { @ P-type gate must not be in psubstrate}
bad_ngate { @ N-type gate must not be in nwell}
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