List of Questions: (click on link to be taken to answer)

	What is Common Mode Range (CMR) and how does it relate to Vin(min) and Vin(max) from the handout?
	What is Slew Rate and how is it used to design an op amp?
	New Guidelines for Design Project Simulation
	In the handout regarding op-amp, positive CMR and negative CMR equations have terms like Vt03(max) and Vt1(min).  What is the difference between Vt0 and these terms for a transistor?
	Should we calculate gain bandwidth from unity gain frequency? Would you please tell how to compute this?
	In the circuit you have given for CMOS operational amplifier,a nMOS   transistor Mb2 and pMOS transistor Mp5 form a current mirror.  Can we form a mirror with two different transistors?
	In writing my report description, I am confused between the difference between Design Methodology and Design Discussion.  What is the difference between both sections since both sections are also discussing thedesign trade offs and design approach?
	Why do my closed loop simulations stop running and fail toconverge?

Question:  What is Common Mode Range (CMR) and how does it relate to Vin(min) and Vin(max) from the handout?

Answer:  CMR specifies the voltage range (max. to min.) that can be applied to both inputs (common) such that the input circuit still performs normally -that is, all the transistors remain in saturation.  If the input voltage is too high, it will start to turn off some of the pMOS transistors, and if it is too low it will start to turn off some of the nMOS transistors.  The exact relation depends on the configuration you have chosen.  You can relate the design project specification for CMR (stated as within 1 V of the supply) to meaning that Vin(min) = 1 V and Vin(max) = 5 V. Also note that I mentioned in class that you might have trouble meeting the 1 volt spec. and that, if you can get within 1.2 volts or so, that will probably be fine also. As with all the design parameters, just do the best you can and specify in your report what you got and why you could not meet the spec. (i.e. explain what factors made it hard/impossible to reach spec.)

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Question:  What is Slew Rate and how is it used to design an op amp?

Answer: Slew Rate (SR) is the rate at which the output voltage changes for a large scale change in voltage at the input. Thus SR is in units of volts/time.  The design project specifies SR is 400nsec for a 1 volt step.  This means that SR = 1V/400nsec = 2.5V/usec.  Note: the slew rate is not a time, but a rate (1/time).

You will use the specification given for slew rate to determine the bias current of the differential stage, since this is the limiting charging time* (see note below).  Thus you can calculate, Ibias > (SR)(Cc) and set Ibias so that it is greater than the product of the slew rate times the compensation capacitance.  This equation is derived from the basic relations of
    Q = C V = I t, where Q is charge and t is time.
When you calculate this value it will be rather small, and I suggest you use a current value slightly larger, maybe even 5-10 times larger, to insure you meet the SR specification.  

If we assume that we are interested in changing the charge to give a 1 volt change in output (as in your design project), then we can calculate each of these to charging times from
    t = Cc/Ibias, for the differential stage
    t = Cl/I6, where Cl is the load capacitor, I6 is the current in the second stage, for the second stage
(Note that both of these equations assume that the node capacitance will be dominated by Cc and Cl, which is generally a good assumption).

Since Ibias is normally much smaller than I6, the slew rate is typically limited by the differential stage and thus we write, SR = Ibias/Cc.  However, you should probably check to see which of these time constants is the largest, and if you find that the second stage stage is longer, then you should adjust the currents so that SR = I6/Cl.

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New Guidelines for Design Project Simulation:  I have discovered that there is a conflict between the models used in B2Spice and the transistor parameters I have given you to use in the design project.   Although this conflict has not been a problem in homework, as your circuits become more complex the conflict will start to cause problems.

If you use this shorter set of parameters and use level 2, everything should work out fine. I have tested a differential amplifier and a cascode amp and everything seems fine.   

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Question: In the handout regarding op-amp, positive CMR and negative CMR equations have terms like Vt03(max) and Vt1(min).  What is the difference between Vt0 and these terms for a transistor?

Answer: The Max and Min of the threshold voltage relate to changes that will occur if there is a bulk-to-source voltage (as related by the GAMMA term).   For your calculations, you may assume that Vto(max) = Vto(min) = Vt

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Question: Should we calculate gain bandwidth from unity gain frequency? Would you please tell how to compute this?

Answer:  You only need to determine the unity gain frequency. The bandwidth is often defined as the unity gain frequency (i.e. BW = wt), but you do not need to discuss that in your project.  

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Question:  In the circuit you have given for CMOS operational amplifier,a nMOS  transistor Mb2 and pMOS transistor Mp5 form a current mirror.  Can we form a  mirror with two different transistors?  In case yes, there will be different  currents in either of them, I suppose.

Answer:  In the circuit shown in the Design Project Description, Mb2 and Mp5 do NOT form a current mirror. Because Vgs(5) is not equal to Vgs(b2), the current will not be mirrored. Instead, the gate voltage of Mb2 provides a bias voltage that will bias the gate of Mp5. By changing the size (W/L) of Mb2 and Mb1 you can adjust the bias voltage on Mp5 to the desired level. In this way it acts somewhat like a resistive divider. Try simulating the bias string by itself (i.e. only transistors Mb1-3) and observe how the voltage at the gate of Mb2 changes as you change the size of the transistors. That is how you set bias voltages on other parts of the circuit.

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Question:  In writing my report description, I am confused between the difference between Design Methodology and Design Discussion.  What is thedifference between both sections since both sections are also discussing thedesign trade offs and design approach?

Answer:  This is a good question and I can see how you might be a bit confused. 

Design Methodology is a brief overview of you APPROACH to designing a circuit that will meet the specifications.  It should contain some brief comments about the theory behind op amp design and possibly some of the more significant equations you used in your initial design.  This section should briefly explain how you set out to accomplish the design task and what parameters you felt were going to create the most constraints in your design.  Thus this section represents your thoughts as you began the design process. 

Design Discussion should be a detailed discussion of your design efforts beyond those covered in the Design Methodology section.   What problems did you have?  What constraints did you find?  What tradeoffs did you encounter?  How did you go about overcoming these problems, constraints, and tradeoffs.  While the Design Methodology section covers your DESIGN APPROACH, the Design Discussion should provide a summary of the actual DESIGN EFFORT and the iterations that followed in order to meet the design goals.  In this section you should show that you learned and understand several of the tradeoffs in designing an op amp.  What adjustments did you make to your initial design to meet specifications, and why did you make them.  Basically, this is the section where you try to show that you know how to design an op amp and that you understand what parts of the circuit to modify to meet each design specification. If there is some overlap between these two sections, that is fine.  But the Design Discussion should contain a lot more detail than the Methodology section.

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Question:  Why do my closed loop simulations stop running and fail toconverge?

Answer:  I can't say why, but here's how to solve it. Thanks to Mark for the solution.

MARK WROTE:  I've figured out how to get around the simulator choking on unity-gain feedback loops.   The solution is to include a .IC (Initial Conditions) statement in the analysis and specify initial voltages for critical nodes. I used the values from the .OP results to set values for all internal nodes not set by voltage sources (see below). Apparently the problem stems from the inability of the simulator to get the circuit to converge. The initial conditions gives it a big, strong "hint" where to start, and it's able to converge.

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