In the circuit above V_dd = 30V and R_g = 10kW. The quiescent operating point is specified to be V_dsq = 20V and the small signal gain v_o / v_g is specified to be -3. The MOSFET is an N channel device with Vtr = 2V, Kp = 60mA / V². You can set the incremental part of the input to zero for the quiescent analysis.

1. Write an expression for the MOSFET's g_m.
2. Write an expression for v_o / v_in in terms of g_m and Rd (the incremental gain).
3. Choose Rd, I_dq, and V_gsq to meet the design requirements.
4. What is the MOSFET's g_m?
5. What is the quiescent power dissipated in the MOSFET?
6. Simulate your design with SPICE. Use a 1V peak input at a frequency of 100kHz and show two cycles. Compute I_dq, V_dq and plot the output voltage. What is the circuits gain?

You are to redesign the circuit to be a logic circuit. Now Vdd = 5V, Vgsq=0 and Vgs = Vin is a 100kHz pulse waveform from 0.3V to 5V. Choose Rd so that with Vin = 5V the output voltage Vds is less than 1V. To see all of the switching details you will need a small tstep, 10ns is small enough. You will also need to save all your points so tmax = tstep.

7. Simulate your design with SPICE. Use a 1ms rise and fall time for your pulse. Plot the input and output voltage for two cycles.
8. Plot the drain current for two cycles. Estimate the average power from V_dd.
9. What kind of logic circuit is this?

In the circuit above V_dd = -30V and R_g = 10kW. The quiescent operating point is specified to be V_dsq = -20V and the small signal gain v_o / v_g is specified to be -3. The MOSFET is a P channel device with Vtr = -2V, Kp = 40mA / V². You can set the incremental part of the input to zero for the quiescent analysis.

1. For the circuit in Fig. 2 write an expression for v_o / v_in in terms of g_m and Rd (the incremental gain).
2. For the circuit in Fig. 2 choose Rd, I_dq, and V_gsq to meet the design requirements.
3. What is the MOSFET's g_m?
4. Simulate your design with SPICE. Use a 1V peak input at a frequency of 100kHz and show two cycles. Compute I_dq, V_dq and plot the output voltage. What is the circuits gain?
5. What happens if the circuit is changed to the one in Fig. 3? What is V_inq and the new gain v_o/v_in keeping the same quiescent operating point?

You are to redesign the circuit in Fig. 3 to be a logic circuit. Now V_dd = 5V, V_inq=0 and V_in is a 100kHz pulse waveform from 0V to 4.7V. Choose Rd so that with V_in = 0V the output voltage V_o is greater than 4V. To see all of the switching details you will need a small tstep, 10ns is small enough. You will also need to save all your points so tmax = tstep.

6. Simulate your design with SPICE. Use a 1ms rise and fall time for your pulse. Plot the input and output voltage for two cycles.
7. Plot the current from the supply for two cycles. Estimate the average power from the supply.
8. What kind logic circuit is this?

V_dd = 5V and V_in is a 100kHz pulse waveform from 0.3V to 4.7V. The N channel MOSFET has parameters Vtr = 2V and Kp = 60mA / V². The P channel MOSFET has parameters Vt = -2V and Kp = 40mA / V². To see all of the switching details you will need a small tstep, 10ns is small enough. You will also need to save all your points so tmax = tstep. If you have Spice convergence problems, go to set simulation options in the simulation menu. Set noopiter=true, gmin=1e-8, reltol=.01, abstol=0.01u, and vntol=1e-2.

1. Simulate the circuit in Fig. 5 with SPICE. Use a 1ms rise and fall time for your pulse. Plot the input and output voltage for two cycles.
2. Plot the current from the supply for two cycles. Estimate the average power from the supply.
3. What kind logic circuit is this?