Navid Yazdi^*, Andrew Mason, Khalil Najafi, and Kensall D. Wise

University of Michigan

Ann Arbor, MI 48109-2122

This paper presents a generic low-power sensor interface circuit compatible with smart microsystems and a wide range of capacitive transducers. The interface chip is highly programmable, can communicate with an external microcontroller using a nine-line sensor bus standard, contains a switched-capacitor readout circuit, supports sensor self-test, and includes a temperature sensor. The circuit can interface with up to six external sensors and contains three internal programmable reference capacitors in the range of 0.15-8pF. The chip measures 3.2mm x 3.2mm in a standard 3µm single-metal double-poly p-well process, dissipates less than 2.2mW from a single 5V supply, and can resolve input capacitance variations of less than 1fF in 10Hz bandwidth.

* Currently with Electrical Engineering Dept., Arizona State University, Tempe, AZ 85287.

As the Micro-Electro-Mechanical Systems (MEMS) industry continues to experience accelerating growth, there has been an obvious trend toward combining MEMS transducers with increasingly sophisticated circuits. One step in this evolution is to integrate circuitry and transducers to form "smart" sensors, yet the low cost and wide availability of present signal processing electronics make it possible to go one step further and form entire smart microsystems. These microsystems, which combine multiple microsensors and/or microactuators with signal processing circuitry on a common substrate, are capable of gathering electronic data from the physical world, processing and acting on the information, and transferring the data to other electronic systems which gain intelligence from this process [1]. It is precisely these capabilities that ensure microsystems will have a pervasive impact on the future of the microelectronics industry in application fields ranging from automotive systems to health care. A significant subset of such microsystems will be small, portable, autonomous units [2,3] that can be distributed to collect data over a long period of time. Because these portable microsystems will be battery powered, one of their key constraints is the overall power consumption, which must be minimized without sacrificing performance. A low-power transducer front-end is vital to this effort, yet most of the devices being manufactured today are piezoresistive and consume large amounts of power. Capacitive microsensors provide an attractive alternative since they dissipate no power and can be read out using relatively low-power circuit techniques while offering high sensitivity and self-test capabilities [4,5]. However, the various capacitive transducers that have been reported display a wide range of base capacitances and sensitivities depending on the technology and structure of each device [6]. This variation among transducers places a challenging requirement on the sensor interface circuit, especially in microsystems with multiple sensors such as the one shown in Fig. 1 [5]. For systems such as this, there is a significant advantage to using a generic interface circuit capable of reading out multiple microsensors, each of which may have a different base capacitance and sensitivity. Furthermore, a generic interface circuit should provide a standard communication link to the main microsystem controller, support sensor self-test and self-calibration, support multi-ranging within a single sensor, dissipate low power, and occupy very small die area with no external components. While numerous readout circuits for capacitive microsensors have been introduced [7-11] and some have even been commercialized [12, 13], to date, a generic interface with all of these features has not been reported. A novel universal transducer interface is reported in [11] that can read out capacitive sensors with a wide range of base capacitances, however it does not support standard communication with a microcontroller, self-test and self-calibration. This paper describes a generic capacitive sensor interface for multi-parameter microsystems which satisfies all the aforementioned requirements. First, a brief description of a microsystem that utilizes this interface circuit is presented to highlight both the requirements and the application of the circuit. Then, the interface chip architecture is presented, followed by a description of its major building blocks. Finally, measurement and test results for the fabricated chip are presented.

The microsystem shown in Fig. 1 utilizes an open architecture with a standard sensor bus which allows the system to be populated with sensors and actuators as required by various applications such as weather monitoring or electronic systems health monitoring for condition-based maintenance. Such applications require that an array of parameters be measured, and the generic capacitive interface chip is a critical component of the overall system because it allows a standard microcontroller to communicate with, and collect data from, a wide variety of sensors. For instance, the currently developed microsystem accommodates sensors for measuring a variety of environmental parameters including temperature, barometric pressure, relative humidity, and acceleration/vibration [4,5]. As shown in Table 1, these sensors display a wide range of base capacitance and sensitivity, which must be covered by the interface chip.

The heart of the microsystem is a microcontroller unit (MCU) that provides stored program control and data handling as well as sensor-specific software routines for in-module sensor calibration, digital compensation, and self-test. The MCU communicates with the front-end transducers via the sensor interface chips and a nine-line sensor bus as illustrated in Fig. 1. Once sensor data has been collected and compensated in-module, it can be stored in-module or output through either a hardwired serial I/O port or an on-board RF transmitter.

The sensor bus is a central part of the microsystem architecture that provides access to multiple sensors/actuators while using a limited number of interconnects. It consists of nine lines: three power leads, four lines for synchronous serial communication, a data output line, and a data valid/interrupt signal [4]. The three power leads are the system supply, ground reference, and a switched reference voltage for devices that can be powered-down during a low-power system sleep mode. For synchronous communication with the front-end devices, chip enable and data strobe signals provide handshaking for use with a programmable-frequency clock and a serial data line. The data out line is used for sensor data output that can be either an analog voltage, a frequency encoded set of pulses, or a serial bitstream. The last line of the sensor bus is data valid, which signals the MCU when valid data is present on the data out line. Data valid is also used as an interrupt from the interface chip that can initiate an event triggered sensor readout when the bus is otherwise idle. This bus is based on a standard used at the University of Michigan and was chosen for its functionality as well as its compatibility with existing systems. Although a variety of bus standards are still being used throughout the sensor industry, this sensor bus provides a reduced line count without requiring complex signal decoding, and it is a predecessor to the very similar and recently adopted IEEE P1451 standard.

Figure 2 shows the block diagram of the interface chip. Communication with the MCU is performed over the sensor bus and is handled by the bus interface unit. Serial data transmitted over the bus is received, decoded, and applied to control various interface chip blocks. The readout circuit utilizes a low-noise front-end charge integrator to read out the difference between the sensor capacitance and a reference capacitor [8]. An input multiplexer enables the chip to interface with up to six capacitive sensors. Furthermore, the chip can be digitally programmed to operate with one of three external and/or internal reference capacitors. The on-chip reference capacitors are laser trimmable in a range of 0.15pF to 8pF in 0.15pF capacitance steps. Programmability of the reference capacitors allows the chip to interface with capacitive sensors having a wide range of base capacitance and also provides input offset control.

The chip analog signal path consists of an input multiplexer, the input charge integrator, a gain stage, an output sample/hold circuit, and an output multiplexer. The gain stage can be programmed on-line to one of three preset gain values each set by laser-trimming. These gains can be used to accommodate sensors with different sensitivities or for multi-ranging a single sensor and can be adjusted by laser trimming the on-chip capacitors. The overall readout sensitivity can be varied from 0.23 mV/fF to 73.5 mV/fF using both digital programming and laser trimming, which gives an effective gain variation from 1 to 312. The output multiplexer provides access to the sensor bus for both the capacitive readout circuitry and the on-chip temperature sensor.

The interface chip also supports self-test and self-calibration. A 3b on-chip DAC can be utilized to generate a variable-amplitude two-phase clock for driving the sense and reference capacitors in each input charge integration cycle. The variable amplitude clock can be used to apply a programmable effective dc voltage and electrostatic force to the sensor for self-test and self-calibration. In self-test mode, the programmable electrostatic force is used to move a sensor structure to generate a change in the sensor's output. In self-calibration mode, the sensor response can be tracked and calibrated while a set of predetermined electrostatic forces are applied. The variable amplitude clock also provides additional control of the overall readout circuit sensitivity by setting the input charge transferred to the front-end charge integrator.

The sensor bus interface unit, illustrated in Fig. 3, handles the communication between the microsystem controller and the capacitive interface chip through the sensor bus. The bus interface unit consists of a series of shift registers that load the input serial data, logic circuitry that decodes incoming instructions, on-chip memory to store data written to the interface chip, and an output multiplexer. Each interface chip contains a 4b laser-programmable chip address and a 4b comparator that checks the chip address of an incoming instruction. The selected chip then loads in a 3b command code and a 5b element address as set by the sensor bus data format, which allows for eight individual commands to be issued to each of 32 read (e.g., sensor) or write (e.g., actuator or memory register) elements. On the generic capacitive sensor interface, during a read command, three of the element address bits are decoded to select one of six external capacitive sensors or the on-chip temperature sensor. The remaining two element address bits are used to select one of three on-chip reference capacitors used by the switched-capacitor readout circuit block. During a write command, data from the microsystem controller is stored in one of three on-chip registers. This data is used to control several other circuit blocks on the chip such as the gain stage of the switched-capacitor readout circuit and the DAC. Based on the input instruction, the output multiplexer selects which sensor data will be put on the shared data out line of the sensor bus and ensures that the output signal is disabled at the end of a sensor read command.

The input switches are controlled so that at each instant only one of the sense capacitors (Cs) and one of the reference capacitors (Cref) are connected to the circuit. During f1, the reset switch of the charge integrator is closed and Cs is charged through the charge integrator output. Once f1 goes low, a packet of charge proportional to the difference between Cs and Cref is integrated on the feedback capacitor of the first stage (Cf1). Meanwhile, the second stage integrator is in reset mode and either Cg1, Cg2, or both Cg1 and Cg2 charge to the output level of the first stage. The gain of the second stage is determined by the ratio of the total capacitance switched into its input to the feedback capacitance (Cf2). Clock phases f3 and f4 are slightly delayed f1 and f2 clocks which become active only when gain 1 or 3 is selected. Similarly, f5 and f6 are delayed f1 and f2 clock phases that are active only when digital gain 2 or 3 is set. Therefore, the gain of the second stage is selected by controlling switching of Cg1 and Cg2 at its input. During f3 (f5) clock phase, the charge stored on Cg1 and Cg2 capacitors is integrated on Cf2. Finally, the output of the second stage is sampled and held at the input of the third stage during fs.

Figure 5 shows the schematic of the opamp used in the switched-capacitor circuit. The opamp is designed to provide low noise and good high frequency PSRR with low power dissipation and to drive capacitive loads over a wide range. Transistors M1-M5 form the input differential stage, with large PMOS transistors (M1-M2) used to reduce noise. The main gain stage is a class AB cascode output stage consisting of M8-M11. The dominant pole is determined by the load capacitance, which eliminates the need for a compensation capacitor and effectively improves the high frequency PSRR. Also, the load capacitance can vary over a wide range without causing stability problems and is driven efficiently by the class AB output stage. The opamp dissipates less than 420µW from a 5V supply and has a slew rate of 1V/µSec with a 50pF capacitive load.

Figure 6 shows a schematic diagram of the self-test current-mode DAC. The 3b DAC consists of three switched current mirrors (Mp0-Mp3) driving an on-chip polysilicon resistor (R) to obtain voltage-mode output. This configuration is used for the DAC due to its simplicity while satisfying the 3b self-testing requirements. The DAC output voltage is buffered and is available at one of the chip output pads. The DAC output also modulates the amplitude of the clocks that drive the sense and reference capacitors ( and ). The amplitude modulation of these clock lines is performed by four transmission-gate switches (S1-S4) which function as a multiplier. An output multiplexer formed by switches (S5-S8) chooses between the amplitude modulated clock lines or the input digital clocks. Hence, when the output multiplexer select line (var) is set, a variable amplitude two phase clock will be provided to the input capacitive sensors. This clock applies an electrostatic force to the input sensors which can be used for self-testing and self-calibration.

To measure temperature in close proximity to the other sensors on the microsystem, a temperature sensor is integrated on the interface chip. This provides data that can be used to digitally compensate for the temperature sensitivity of any other sensors connected through this interface chip. The temperature sensor exploits the temperature dependence of the drain current of an MOS transistor in weak inversion [15] as shown in Fig. 7. Here, the charging current of the capacitively-loaded ring oscillator input stage is set by a PMOS transistor biased for subthreshold operation. Feedback from the ring oscillator is used to discharge the input capacitor and maintain the oscillation. Since the charging current is temperature dependent, the frequency of the oscillator provides a measure of the local temperature. While many integrated circuit temperature sensors exist [16], this technique was selected because it provides a direct digital output with a low-power circuit that is accurate enough (± 1° C) to compensate the temperature dependence of other transducers in the system. In addition, it can easily be implemented in a standard CMOS process and does not require any bipolar devices.

The chip has been fabricated using a standard 3µm, single metal, double poly, p-well, CMOS process at the University of Michigan [17]. Figure 8 shows a photograph of the chip, which measures 3.2mm x 3.2mm and dissipates less than 2.2mW from a single 5V supply. Approximately 85% of the power dissipation is due to the quiescent currents of the five opamps integrated on the chip. Table 2 summarizes the chip specifications. Test results have shown full circuit functionality with an input capacitance resolution better than 1fF in 10 Hz bandwidth, and a maximum readout clock rate of 50kHz. Although carefully sized dummy switches are used in the switched-capacitor circuit, the resolution is still limited by the clock switching noise rather than kT/C and input amplifier flicker noise. Figure 9 shows the output of the charge integrator with a 6pF reference capacitor as the sensor capacitance is varied from 3pF to 8pF. Figure 10 illustrates the output of the readout circuit as the input capacitance changes in 0.5pF steps. Programmability of the gain is illustrated in Fig. 11, where the measured output is plotted for various digital gain selections of 2.66, 6, and 8.66.

The temperature dependence of the readout circuit offset and sensitivity has been measured over the range from 0 to 60° C. The circuit sensitivity is not significantly affected by its operating temperature and in all measurements the temperature dependence of the output voltage has been dominated by that of offset. The main source of offset temperature dependence is due to junction leakage current of the reset switches in parallel with the charge integrating capacitors and the first stage opamp offset. The maximum temperature dependence of offset is equivalent to less than 0.16fF/° C input-referred capacitance. Note that the temperature dependence of the readout circuit does not adversely affect the performance of the overall microsystem since it can easily be compensated as temperature compensation of the sensor is performed using the on-chip temperature sensor data and the microcontroller of the system.

The temperature sensor was tested over the range of -20ºC to 60ºC and the output oscillation period was measured. The results for a representative device are plotted in Fig. 12 which illustrates a sensitivity from 4msec/° C at high temperatures to 33msec/° C at low temperatures. A device tested for one month demonstrated a stable resolution better than 1° C over its entire range of operation. In order to calibrate the temperature sensor, the non-linear response is approximated by nine piecewise linear intervals as shown in Fig. 12. Using this method, the temperature is obtained by evaluating a linear equation in-module, the slope and y-intercept of which are determined by the measured sensor output frequency. This provides a temperature measurement accurate to within ± 1° C that is stored in the microsystem controller and used to digitally compensate other sensors for temperature cross sensitivities. In all tested cases, this accuracy was adequate for digital compensation using polynomial evaluation.

The microsystem shown in Fig. 13 is an example of a multi-parameter sensing system in which the generic capacitive sensor interface chip plays a key role [5]. This microsystem utilizes four interface chips to link a commercially available MCU to twenty-two sensor elements for measuring temperature, pressure, humidity, and acceleration [4,5]. The interface chip can operate with a sensor bus clock speed up to 10MHz. With a minimum of 12b required for an input read command, the instruction can be issued in less than 2µSec including time for the strobe and chip enable signals. The bus clock speed of the implemented microsystem is 1MHz bounded by the system microcontroller (MCU) speed. The maximum speed for issuing consecutive read commands in the microsystem is slightly greater than 10kHz, which is mainly limited by the switched-capacitor readout circuit, the MCU and interface chip communication, and off-chip A/D conversion. If additional commands (such as gain selection or DAC settings) to the interface chip are required, an additional 2-3µSec is necessary, but a 10kHz readout speed could still be maintained.

In this paper a generic interface circuit for capacitive sensors for smart multielement microsystems has been presented. This chip satisfies all the requirements of such microsystems: It can interface with a large variety of capacitive sensors with base-capacitance and sensitivity spread over a wide range, supports communication with any microcontroller over a standard sensor bus, has programmable gain and offset control, and supports sensor self-test. In addition the interface circuit integrates a temperature sensor on-chip. It dissipates less than 2.2mW from a single supply, resolves input capacitance variations better than 1fF in 10 Hz bandwidth, and has a 1° C temperature resolution. A number of these generic capacitive interface circuits are currently employed in a low-power wireless multielement microsystem for environmental monitoring. While this wireless battery-powered system provides a prototype for future small portable microsystems, the presented generic interface chip and its combined features will be essential for the successful realization of similar microsystems of the future. The steady push toward low-power high-performance electronics, combined with the increasing attention being given to MEMS-based microsystems, will likely lead to improved versions of the interface chip that still need to combine and implement many of the same functions. Future designs are expected to have expanded range and programmability (to improve gain and offset trim resolution), as well as improved bus interface modules with more on-chip memory and the ability to interface with a larger number of sensors and actuators.

The authors would like to thank Dr. Chingwen Yeh for the CMOS circuit fabrication and Mr. Babak Amirparviz for some of the measurements. Also, the help of the staff and students of the Center for Integrated Sensors and Circuits at the University of Michigan is gratefully acknowledged. This work was supported by the Defense Advanced Research Projects Agency under contract JFBI 92-149 and in part by K. Najafi’s NSF-NYI grant #ECS-925 7400.

Table 1: Base capacitance and sensitivity of several sensors employed in the microsystem.

Table 2: Summary of interface chip specifications.

Figure 1: Block diagram of a microsystem that utilizes the generic capacitive sensor interface chip and multiple microsensors to measure a variety of physical parameters.

Figure 2: Block diagram of the capacitive sensor interface chip.

Figure 3: Diagram of the sensor bus interface unit of the capacitive sensor interface chip.

Figure 4: Schematic diagram of the switched-capacitor readout circuit.

Figure 5: Schematic diagram of the low noise operational amplifier used in the readout circuit front-end.

Figure 6: Schematic diagram of self-test digital-to-analog converter.

Figure 7: A temperature sensitive oscillator used to measure temperature in close proximity to the other sensing elements on the microsystem.

Figure 8: Die photograph of the generic capacitive sensor interface.

Figure 9: Upper trace: Reset control of the input charge integrator; Lower trace: Output of the charge integrator with a 6pF reference capacitor as the sensor capacitance changes from 3pF to 8pF.

Figure 10: Readout circuit output as the input capacitance changes in 0.5pF steps; No laser trimming for gain adjustment is performed and lowest second-stage gain is selected.

Figure 11: Measured output of the chip as a function of the input capacitance for different second-stage gain settings. The three programmed gains are: G1=2.66, G2=6, and G3=8.66.

Figure 12: Measured response of the temperature sensor. Also shown are the linear approximations used to calibrate the sensor in steps of 10ºC.

Figure 13: Photograph of a working microsystem for environmental monitoring that uses several generic capacitive sensor interface chips.